Review Article
This article belongs to the Special Issue No. 1, 2026 on Security 4.0 – Cybersecurity and Digital Resilience of Information Systems (CYRES 2026)
R. Pilipović, “Domain-Specific Accelerators for Post-Quantum Cryptography,” International Journal of Innovative Solutions in Engineering, no. S1, pp. 98–109, Oct. 2026, doi: 10.47960/3029-3200.2026.S1.98.
pages 98-109
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Abstract
The advent of large-scale quantum computing threatens the public-key infrastructure that secures modern digital communication, as Shor’s algorithm renders the integer-factorization and discrete-logarithm problems underlying RSA and elliptic-curve cryptography tractable. In response, the National Institute of Standards and Technology (NIST) has standardized a first generation of quantum-resistant digital signature algorithms, namely the lattice-based CRYSTALS-Dilithium (ML-DSA, FIPS 204) and Falcon (FN-DSA) and the hash-based SPHINCS+ (SLH-DSA, FIPS 205). These schemes impose far higher computational and memory costs than their classical counterparts, which motivates domain-specific hardware accelerators able to meet the performance and energy budgets of practical systems. This survey reviews domain-specific accelerators for post-quantum signatures, giving equal attention to the three standardized schemes. For each, we examine the underlying construction, its parameter sets, and, above all, the implementation challenges that shape its hardware, from the rejection sampling of Dilithium to the floating-point Gaussian sampling of Falcon and the hashing-bound datapath of SPHINCS+. We compare reported FPGA and ASIC accelerators for every scheme, present a general-purpose accelerator template, and outline the emerging schemes and open challenges that will guide future hardware design.
Keywords
Post-Quantum Cryptography, Digital Signatures, Hardware Accelerators, FPGA, Falcon, Dilithium.
ijise ID
32
Publication Date
In Press
References
- P. W. Shor, “Polynomial-Time Algorithms for Prime Factorization and Discrete Logarithms on a Quantum Computer,” SIAM J. Comput., vol. 26, no. 5, pp. 1484–1509, Oct. 1997, doi: 10.1137/S0097539795293172.
- L. Chen et al., “Report on post-quantum cryptography,” NIST, Gaithersburg, MD, USA, NISTIR 8105, 2016.
- National Institute of Standards and Technology, “Module-lattice-based digital signature standard,” FIPS 204, 2024.
- National Institute of Standards and Technology, “Stateless hash-based digital signature standard,” FIPS 205, 2024.
- P.-A. Fouque et al., “Falcon: Fast-Fourier lattice-based compact signatures over NTRU,” Submission to the NIST PQC standardization process, 2020.
- S. Bai et al., “CRYSTALS-Dilithium: Algorithm specifications and supporting documentation,” Submission to the NIST PQC standardization process, 2021.
- D. J. Bernstein, A. Hülsing, S. Kölbl, R. Niederhagen, J. Rijneveld, and P. Schwabe, “The SPHINCS+ Signature Framework,” in Proceedings of the 2019 ACM SIGSAC Conference on Computer and Communications Security, London United Kingdom: ACM, Nov. 2019, pp. 2129–2146. doi: 10.1145/3319535.3363229.
- O. Regev, “On lattices, learning with errors, random linear codes, and cryptography,” J. ACM, vol. 56, no. 6, pp. 1–40, Sep. 2009, doi: 10.1145/1568318.1568324.
- C. Gentry, C. Peikert, and V. Vaikuntanathan, “Trapdoors for hard lattices and new cryptographic constructions,” in Proceedings of the fortieth annual ACM symposium on Theory of computing, Victoria British Columbia Canada: ACM, May 2008, pp. 197–206. doi: 10.1145/1374376.1374407.
- A. Aikata, A. C. Mert, M. Imran, S. Pagliarini, and S. S. Roy, “KaLi: A Crystal for Post-Quantum Security Using Kyber and Dilithium,” IEEE Trans. Circuits Syst. I, vol. 70, no. 2, pp. 747–758, Feb. 2023, doi: 10.1109/TCSI.2022.3219555.
- M. Bisheh-Niasar, E. Karabulut, K. Upadhyayula, M. Norris, and B. Pillilli, “Adams Bridge accelerator: Bridging the post-quantum transition,” IACR Cryptol. ePrint Arch., 2026/256.
- Y. Ouyang et al., “FalconSign: An Efficient and High-Throughput Hardware Architecture for Falcon Signature Generation,” TCHES, vol. 2025, no. 1, pp. 203–226, Dec. 2024, doi: 10.46586/tches.v2025.i1.203-226.
- P. Karl, J. Schupp, and G. Sigl, “Performance and Communication Cost of Hardware Accelerators for Hashing in Post-Quantum Cryptography,” ACM Trans. Embed. Comput. Syst., vol. 24, no. 5, pp. 1–31, Sep. 2025, doi: 10.1145/3676965.
- National Institute of Standards and Technology, “Status report on the second round of the additional digital signature schemes for the NIST post-quantum cryptography standardization process,” NISTIR 8610, 2026.
- V. Smole, A. Aikata, R. Pilipovic, and S. S. Roy, “Giving Falcon Its Wings: Fast Hardware Acceleration for Signing and Verification Using FN-DSA,” IEEE Trans. Circuits Syst. I, vol. 73, no. 9, pp. 6101–6114, Sep. 2026, doi: 10.1109/TCSI.2026.3705146.
- M. Schmid, D. Amiet, J. Wendler, P. Zbinden, and T. Wei, “Falcon takes off: A hardware implementation of the Falcon signature scheme,” IACR Cryptol. ePrint Arch., 2023.
- L. Beckwith, D. T. Nguyen, and K. Gaj, “High-Performance Hardware Implementation of CRYSTALS-Dilithium,” in 2021 International Conference on Field-Programmable Technology (ICFPT), Auckland, New Zealand: IEEE, Dec. 2021, pp. 1–10. doi: 10.1109/ICFPT52863.2021.9609917.
- S. Pendyala, R. Magesh, E. B. Kavun, and A. Aysu, “Accelerating FALCON: Speed records for FALCON’s SamplerZ on Xilinx FPGAs,” IACR Cryptol. ePrint Arch., 2025/1490.
- X. Yu, Y. Sun, Y. Zhao, H. Kuang, and J. Han, “RVCE-FAL: A RISC-V Scalar-Vector Custom Extension for Faster FALCON Digital Signature,” in 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), Valencia, Spain: IEEE, Mar. 2024, pp. 1–6. doi: 10.23919/DATE58400.2024.10546713.
- T.-T. Nguyen, D.-D. Nguyen, T.-T. Dao, and N.-Q. Luc, “Implementation Efficiency of Falcon Digital Signature Scheme on Arty-7 XC7A35T Board,” Electronics, vol. 14, no. 22, p. 4504, Nov. 2025, doi: 10.3390/electronics14224504.
- S. Ricci et al., “Implementing CRYSTALS-Dilithium Signature Scheme on FPGAs,” in Proceedings of the 16th International Conference on Availability, Reliability and Security, Vienna Austria: ACM, Aug. 2021, pp. 1–11. doi: 10.1145/3465481.3465756.
- G. Land, P. Sasdrich, and T. Güneysu, “A Hard Crystal – Implementing Dilithium on Reconfigurable Hardware,” in Smart Card Research and Advanced Applications, V. Grosso and T. Pöppelmann, Eds., Cham: Springer International Publishing, 2022, pp. 210–230. doi: 10.1007/978-3-030-97348-3_12.
- Q. Norga, S. Kundu, and I. Verbauwhede, “ML-DSA-OSH: An Efficient, Open-Source Hardware Implementation of ML-DSA,” in 2026 Design, Automation & Test in Europe Conference (DATE), Verona, Italy: IEEE, Apr. 2026, pp. 1–3. doi: 10.23919/DATE69613.2026.11539720.
- D. Amiet, L. Leuenberger, A. Curiger, and P. Zbinden, “FPGA-based SPHINCS+ implementations: Mind the glitch,” in Proc. IEEE Int. Symp. Hardware Oriented Security and Trust (HOST), 2020.
- Q. Berthet, A. Upegui, L. Gantel, A. Duc, and G. Traverso, “An area-efficient SPHINCS+ post-quantum signature coprocessor,” in Proc. IEEE Int. Parallel and Distributed Processing Symp. Workshops (IPDPSW), 2021.
- S. Deshpande, Y. Lee, C. Karakuzu, J. Szefer, and Y. Paek, “SPHINCSLET: An Area-Efficient Accelerator for the Full SPHINCS+ Digital Signature Algorithm,” ACM Trans. Embed. Comput. Syst., vol. 24, no. 5, pp. 1–19, Sep. 2025, doi: 10.1145/3728469.
- National Institute of Standards and Technology, “Module-lattice-based key-encapsulation mechanism standard,” FIPS 203, 2024.
- L. Groot Bruinderink and P. Pessl, “Differential Fault Attacks on Deterministic Lattice Signatures,” TCHES, pp. 21–43, Aug. 2018, doi: 10.46586/tches.v2018.i3.21-43.
- J. W. Bos, M. Gourjon, J. Renes, T. Schneider, and C. Van Vredendaal, “Masking Kyber: First- and Higher-Order Implementations,” TCHES, pp. 173–214, Aug. 2021, doi: 10.46586/tches.v2021.i4.173-214.
- T. Espitau, P.-A. Fouque, B. Gérard, and M. Tibouchi, “Loop-Abort Faults on Lattice-Based Fiat-Shamir and Hash-and-Sign Signatures,” in Selected Areas in Cryptography – SAC 2016, vol. 10532, R. Avanzi and H. Heys, Eds., Cham: Springer International Publishing, 2017, pp. 140–158. doi: 10.1007/978-3-319-69453-5_8.
- V. Migliore, B. Gérard, M. Tibouchi, and P.-A. Fouque, “Masking Dilithium: Efficient Implementation and Side-Channel Evaluation,” in Applied Cryptography and Network Security, vol. 11464, R. H. Deng, V. Gauthier-Umaña, M. Ochoa, and M. Yung, Eds., Cham: Springer International Publishing, 2019, pp. 344–362. doi: 10.1007/978-3-030-21568-2_17.
